NVIDIA Deep Learning Accelerator. Hardware logic implementing different function engines.
Deep Learning Accelerator
User Mode Driver, software running in user space. It provides interfaces to user application
Kernel Mode Driver, software running in kernel space. It implement low level functions such as hardware programming and provides interfaces to UMD
Format used to store compiled neural network.
One complete hardware block processing. It starts with a set of register configuration with an enable field. When it is done, it triggers ONE interrupt.
Single data processor, a functional sub unit in NVDLA engine
Planar data processor, a functional sub unit in NVDLA engine
Channel data processor, a functional sub unit in NVDLA engine
Data operation processor. A functional sub unit in NVDLA engine to support data layout transformation
Bridge DMA. BDMA transform data from CVSRAM to MC and vice versa
Convolution DMA, responsible for load image/weight/feature data to convolution core
Read DMA, instanced in SDP/CDP/PDP/Rubik engines which responsible for load input data from external memory (either MC or CVSRAM)
Write DMA, instanced in SDP/CDP/PDP/Rubik engines and responsible for write output data to external memory (either MC or CVSRAM)
Control backbone. System control data path that connected to NVDLA
Data backbone. The memory system that to which NVDLA connects
ARM Advanced Microcontroller Bus Architecture. A set of ARM defined bus standards.
Advanced eXtensible Interface. The third generation of AMBA interface defined in the AMBA 3 specification.
Convolutional Neural Network. A class of artificial neural networks.
Configuration Space Bus. (See External Interfaces.)
Data Back Bone – the path that NVDLA uses to perform DMA to system memory, such as the DRAM interface.
The NVDLA interface to the DBB. (See External Interfaces.)
Interrupt request. (See External Interfaces.)
NVIDIA Deep Learning Accelerator.
The NVDLA interface to an optional high-performance SRAM subsystem.